Intel's 'Knights Corner' chip hits supercomputing speed

[A chauhan]

The processor, designed for high-performance apps, can run at 1 teraflop
By Patrick Thibodeau
November 16, 2011 06:06 AM ET

Computerworld - SEATTLE -- Intel has produced a new chip that can operate at a sustained speed of one teraflop -- the type of supercomputing speed the U.S. government paid $55 million for 15 years ago. A teraflop is one trillion calculations per second.

This chip, called Knights Corner, was shown for the first time at the SC11 supercomputing conference here.

Intel isn't yet releasing all of the specs on the processor, including the amount of power it uses or its exact number of cores (it's more than 50). But the chip already has one large customer and a delivery date to make next year.

Rajeeb Hazra, general manager of Technical Computing at Intel, introduced the physical chip with a bit of flourish in the basement of a steak house here, holding it up. "It's not a PowerPoint, it's a real chip," he said.

There was a live feed showing the chip's performance as it ran a Linux workload from a "secure location" (hotel room) that attendees were later shown.

Intel didn't specify exactly when Knights Corner will be commercially available, although it has at least one customer, the Texas Advanced Computing Center. The Austin-based facility will begin installing the system next year with full operation expected in 2013. It will initially run at 10 petaflops.

One way to understand the performance of Intel's Knights Corner is to measure it through time.

In 1997, ASCI Red at Sandia National Lab broke the teraflop barrier, using almost 10,000 Pentium chips to reach one trillion calculations per second. Total development cost was $55 million.

In 2008, IBM's Roadrunner system at Los Alamos National Labs achieved petaflop speeds for the first time. That's 1,000 trillion (one quadrillion) sustained floating point operations per second.

Computer makers need to find new ways to offer compute power at low power if they are going to reach exascale computing speeds in the next decade. Exascale is 1,000 times more powerful than a petaflop.

The new Intel chip is based on Intel's MIC (Many Integrated Core) architecture, and, similar to GPUs, is a 64-bit co-processor designed to handle highly parallel applications.

"The MIC processor ought to be easier to program because they use the same instruction set architecture as Intel x86 processors," said Steve Conway, an analyst at IDC.

"As [high-performance computing] approaches the exascale era, more and more systems will exploit a mix of x86 processors and accelerators," said Conway.

While Intel has produced chips previously that can break one teraflop, it has not made one for production.

A major competitor to Intel's approach is coming from Nvidia GPUs. That company is exploring ways to integrate ARM CPUs, widely used in cell phones, with GPUs.

Robert Harrison, director of the Joint Institute for Computational Sciences at Oak Ridge National Laboratory, has been using an earlier version of the MIC processor, and said its advantage is in its programming. It uses the same software stack and compilers as the x86 system.

"You can focus on tuning and optimizing rather than having the daunting task of porting everything manually from scratch into a new environment,' said Harrison.

Intel's 'Knights Corner' chip hits supercomputing speed - Computerworld

Exciting news 8)

 

[A chauhan]

Intel Announce Knight's Corner, 22nm, 50 Cores

Fancy a processor with 1 teraflop of processing power in your PC? Intel have today unveiled their new Knight's Corner chip that uses a 22nm build process to pack a huge 50 cores onto the die. This new (MIC) Many Integrated Core chip isn't for playing Battlefield 3, frankly it would be wasted on that. Instead this chip will be used solely for special scientific and engineering research into subjects like weather modelling, protein folding and cancer research.

What it means though is a huge leap forward in processing power and this can have the benefits of enabling supercomputers to perform vastly more calculations per second than are currently available, or for far smaller supercomputers to be constructed that would not only be considerably cheaper than today's machines, but that would also consume much less electricity.

As and when this technology filters down towards the consumer level this will mean smaller and much more energy-efficient datacentres and rack servers that can support up to fifty virtualised environments simultaneously.

...The next generation of processors for PCs will also be based on a 22nm manufacturing process that will make them faster and considerably more power-efficient. Every generation of processors now consume much less energy than the ones before them and a processor has even been demonstrated now that consumes less power when working flat out than a standard PC chip today does when in standby....

for full news go here- Intel Announce Knight's Corner, 22nm, 50 Cores

 

[The Messiah]

My 6600 quad core is still going strong.

 

[A chauhan]

Intel Says 'Knights Corner' Xeon Chips Ready For 2012
By Kristin Bent, CRN
June 18, 2012 5:43 PM ET

Intel announced Monday at the International Supercomputing Conference in Hamburg, Germany, its first-generation Xeon Phi family of coprocessors, codenamed "Knights Corner."

The new chips, aimed to complement Intel's existing Xeon processor E5 lineup, are said by the chip maker to pave the way for new high-performance computing platforms that can break the exaflop barrier by 2018.

The upcoming 22-nm Xeon Phi series, slated to launch by the end of the year, will be the first commercial processors from Intel based on its Many Integrated Core (MIC) architecture. The MIC model means the new chips will be optimized for highly parallel workloads, such as those handled by supercomputers or high-performance computing (HPC) systems, and will be able to accelerate data-intensive applications like weather modeling or advanced materials simulation.

Containing more than 50 cores and hosting a minimum of 8 GB of GDDR5 memory, the Xeon Phi family is being positioned by Intel as a stepping stone toward its goal of reaching exascale computing over the next six years. Achieving this goal would yield a new generation of supercomputers capable of reaching processing speeds nearly 100 times as fast as the world's most sophisticated supercomputers can process data today.

It would also enable more complex calculations, making it possible, for example, for scientists to produce a two-week weather forecast just as accurately as they produce a 48-hour forecast today.

"As we add Intel Xeon Phi products to our portfolio, scientists, engineers and IT professionals will experience breakthrough levels of performance to effectively address challenges ranging from climate change to risk management," said Raj Hazra, Intel Corporation vice president and general manager of the Technical Computing at Data Center and Connected Systems Group, in a statement. "This is the next step of Intel's commitment to achieve exascale-level computation by 2018, and create a unique technology category that delivers unprecedented performance for today's highly parallel applications."

Xeon Phi shipments are planned for the second half of 2012, but the first development cluster based on the new coprocessors is already running and has been ranked 150th on the Top500 list of supercomputers, Intel said. The system delivers up to 118 teraflops of performance.

The Santa Clara, Calif.-based chip giant also said 44 manufacturers including Bull, Cray, Dell, HP, IBM, Inspur, SGI and NEC have already committed to including Xeon Phi chips in their system roadmaps.

In a separate announcement from the ISC event Monday, Intel revealed it was acquiring roughly 1,700 patents and patent applications from wireless technologies vendor InterDigital. The deal, which is valued at $375 million, will arm Intel with patents related to 3G, 4G and 802.11 technologies it can use to expand its footprint in the mobile market.
http://www.crn.com/news/components-...;jsessionid=32h8zSg0BsxrkKNHu2VzBg**.ecappj02

 

[Mad Indian]

^^^ Will it be available for gaming

 

[A chauhan]

^^ If released for PC you will surely be able to use it for gaming, perhaps you will get your answer by year's end.

Intel Open-Sources "Knights Corner" Linux Code
Posted by Michael Larabel on June 13, 2012
Intel has published open-source code for supporting the Knights Corner micro-architecture on Linux.

Last week Intel pushed out code for Knights Corner, but up to now it seems the Linux support has been largely unnoticed. Knights Corner is the 22nm successor to Knights Ferry and part of Intel's Many Integrated Core (MIC) Architecture that is derived from their Larrabee project back in the day. Intel Knights Corner hardware should begin surfacing in the coming months in limited quantities and will feature 50+ cores per chip. Early hardware of Knights Corner has been shown going back to last November.

On the 5th of June, the first open-source Linux code for Knights Corner was published. The software stack consists of embedded Linux, a modified GCC compiler, and a software driver. Intel's also modified GDB for Knights Corner debugging support. Intel calls this Knights Corner stack the MPSS, short for the "Intel Many Integrated Core (MIC) Platform Software Stack." This stack uses the Linux 2.6.34 kernel and is tested against Red Hat Enterprise Linux 6 and SuSE Linux Enterprise Server 11.

As far as what the code does, "The open source updates we have made are in support of the instruction set, the ABI, initializing and controlling an SMP on-a-chip, and the glue software to support the coprocessor communication with the host system. The Symmetric Communications Interface (SCIF) is included in the RPM bundle. SCIF provides a mechanism for inter-node communications within a single platform. A node, for SCIF purposes, is defined as either a Knights Corner device or the Intel Xeon processor. In particular, SCIF abstracts the details of communicating over the PCI Express bus. The SCIF APIs are callable from both user space (uSCIF) and kernel-space (kSCIF)."

The GCC changes work for the Knights Ferry prototype board or the Knights Corner co-processor. However, not supported right now is the Knights Corner vector instructions and optimization improvements. "GCC for Knights Corner is really only for building the kernel and related tools; it is not for building applications. Using GCC to build an application for Knights Corner will most often result in low performance code due its current inability to vectorize for the new Knights Corner vector instructions. Future changes to give full usage of Knights Corner vector instructions would require work on the GCC vectorizer to utilize those instructions' masking capabilities. This is something that requires a broader discussion in the GCC community than simply changing the code generator."

Linux kernel changes to enable Knights Corner include "little changes" for supporting the Intel Pentium processor core with 64-bit and special vector instructions, power management support, and introducing the Knights Corner machine check architecture. Much of the other Knights Corner Linux kernel code reuses the Intel Pentium processor support code.

Additional information on the Knights Corner open-source code drop is available from this Intel.com blog post.

There's also a separate blog post on the Knights Corner micro-architecture support. Below are some quotes from that posting.

- "The software stack download includes source for an embedded Linux environment which runs on Knights Corner coprocessors along with the driver code that connects Knights Corner coprocessors to a host processor. To build this code stack, we have included a minimally modified GCC compiler. To support application development, we have enabled GDB. This is just the beginning! The Intel Parallel Studio XE and Intel Cluster Studio XE products for Linux are also entering public field-testing, including support for Knights Corner coprocessors. These high-performance, familiar and popular tools simply support Knights Corner as another target without requiring new tools or separate product purchases. A number of other vendors are working on their support for Knights Corner as well in their familiar and popular products."

- "The MIC architecture is specifically designed to provide the programmability of an SMP system while optimizing for power efficiency and highly parallel workloads. Knights Corner is the first product to use this architecture and deliver on this exciting vision. It's an SMP on-a-chip."

- "This combination of Linux, 64-bits, and new vector capabilities with an Intel® Pentium® processor-derived core, means that Knights Corner is not completely binary compatible with any previous Intel processor."

- "Knights Corner is a coprocessor so it lives in a system with a regular "host" processor that boots up the overall system and orders the coprocessor around. This is a product design, not an architectural feature. While it is an SMP-on-a-chip, we can think of Knights Corner as an embedded system from the standpoint of the operating system. Therefore, Knights Corner boots and runs an embedded Linux kernel and is connected to the main system through enabling software which lives in drivers on both the host system and the embedded system. The changes to open source components are in support of the instruction set choices, the ABI, initializing and controlling an SMP on-a-chip, and the enabling software to support the coprocessor communication with the host system."

Fun Fact: One of the original developers on the Larrabee project who was working on the software stack was Mike Sartain via RAD Game Tools, who is now at Valve and one of the developers heavily involved with the Steam / Source Engine Linux client efforts. Michael Abrash was also involved with Larrabee and is also at Valve, but working on other projects.
[Phoronix] Intel Open-Sources "Knights Corner" Linux Code

 

[A chauhan]

Intel could kill performance PC graphics in 2015

Opinion Is it the end for discrete graphics?

By Jeremy Laird July 18th,

Visual computing. Remember that? It was the buzzphrase from Intel's IDF shindig in San Francisco in 2008. No, I can't remember that far back either. I had to leaf through the dusty TechRadar annals to dig up the date.

Of course, the next big thing for Intel back then as well as being one of the supposed main drivers of visual computing was the ill-fated Larrabee graphics chip. It looked extremely exciting at the time, what with its programmable architecture and x86 origins.

But it was an idea ahead of its time. PC graphics, it turns out, is pretty competitive. And Larrabee wasn't up to snuff. So it got nixed. Or rather it morphed into a co-processor for highly parallelised industry computing.

As far as I'm aware, nobody has really been buying Larrabee based products as yet. It's still in the evaluation phase with a commercial product, codenamed Knights Corner and to be sold under the Xeon Phi brand, due out later this year or maybe 2013.
Ye olde Larrabee

But that doesn't matter. What does is that the brave new world of vector-accelerated visual computing promised by Larrabee is still on Intel's roadmap for desktop PCs and it may yet have a huge impact on your computing experience, but perhaps not as you'd imagined.

There are three closely linked issues in play here. One is the question of when, if ever, integrated graphics will ever be good enough for high quality gaming. The other is whether today's model of discrete CPU and graphics chip will be entirely usurped by system-on-a-chip (SoC) designs before that can happen. The last is whether Intel will still support discrete graphics for consumer PCs when it does.

What we can say for certain is that none of this will happen with Intel's next big architectural shift, known as Haswell. You can read all about Haswell shortly in a TechRadar deep dive written by yours truly, so keep your scanners peeled for that.

But in this context, Haswell doesn't do anything all that exciting in terms of either graphics or integration for desktop PCs. It has much more powerful 3D hardware. But it's largely the same old GenX architecture as seen in the current Intel HD Graphics, just with a load more cores.
Haswell, Broadwell and Skylake

The follow up to Haswell is Broadwell, which is essentially a 14nm die shrink of 22nm Haswell as decreed by Intel's Tick-Tock new-architecture-then-die-shrink development cadence, as the marketing patois goes.

That means it carries over the Haswell graphics architecture. It's no child of Larrabee, in other words. However, it is taking a step closer to SoC status by moving the PCH chip (otherwise known as the southbridge) onto the CPU package for all consumer models (some Haswell chips for ultrabook PCs will also have the PCH inside the CPU package).

Where things get really interesting, however, is the next chip along the line, known as Skylake, due out 2015. Now, it's a little too far out for any of this to be set in stone. But my understanding is that Skylake will be both a true single-chip SoC and finally deliver on the Larrabee promise of a fully flexible graphics pipeline and one that blurs the line between CPU and GPU.

The question is, with Skylake's greater level of integration, will Intel leave the door open for attaching ultra high bandwidth peripherals, ie graphics cards? Or will it take the unilateral decision that its integrated graphics is good.

Intel could kill performance PC graphics in 2015 | News | TechRadar

 

[Predator]

Rajeeb Hazra, general manager of Technical Computing at Intel, introduced the physical chip with a bit of flourish in the basement of a steak house here, holding it up. "It's not a PowerPoint, it's a real chip," he said.

Rajeeb Hazra | LinkedIn
Education
* Jadavpur University

:thumb:

 

[Predator]

^^^ Will it be available for gaming

No, its mentioned in the article

This new (MIC) Many Integrated Core chip isn't for playing Battlefield 3, frankly it would be wasted on that. Instead this chip will be used solely for special scientific and engineering research into subjects like weather modelling, protein folding and cancer research.